PERMANENT MAGNET SYNCHRONOUS MOTOR (PMSM) HAS GAINED MORE INTEREST RECENTLY IN INDUSTRIAL APPLICATIONS. DIGITAL HARDWARE SOLUTIONS SUCH AS FIELD PROGRAMMABLE GATE ARRAYS (FPGAS) ARE THE MOST PREFERRED METHODS FOR CONTROLLING PMSM DRIVERS. THIS PAPER PRESENTS AN IMPLEMENTATION OF A Current CONTROL SYSTEM FOR PMSM BASED ON FPGA. ENCODER-BASED SPEED AND POSITION DETECTION METHOD HAS BEEN USED IN PROPOSED HARDWARE. THE WHOLE SYSTEM HAS BEEN MODELED AND SIMULATED IN SYSTEM LEVEL USING MATLAB/SIMULINK. HARDWARE ARCHITECTURE FOR ALL COMPUTATIONAL BLOCKS IS IMPLEMENTED USING VERILOG HDL. THE HARDWARE ARCHITECTURE HAS BEEN SUCCESSFULLY SYNTHESIZED AND IMPLEMENTED ON ALTERA CYCLONE II FPGA. PROPOSED SYSTEM ARCHITECTURE AND COMPUTATIONAL BLOCKS ARE DESCRIBED AND SYSTEM LEVEL AND RTL SIMULATION RESULTS ARE PRESENTED. SIMULATION RESULTS SHOW THAT THE TOTAL COMPUTATION CYCLE TIME OF IMPLEMENTED SYSTEM ON ALTERA CYCLONE II FPGA IS 456NS.

IN IRAN POWER NETWORK ESPECIALLY IN TEHRAN REGIONAL ELECTRIC COMPANY LIKE OTHER POWER SYSTEMS, SHORT-CIRCUIT Current INCREASES BY EXTENSION OF THE ELECTRICAL POWER SYSTEM BECAUSE OF RISING DEMAND OF ELECTRICAL POWER. THIS FAULT Current MAGNITUDE IS MORE THAN THE CIRCUIT BREAKER INTERRUPTING RATINGS ESPECIALLY IN MONTAZERQAEM POWER PLANT. FAULT CurrentS HAVE A GREAT INFLUENCE ON POWER SYSTEM. FOR REDUCING THESE RISKS, SOME EXPENSIVE OR COMPLICATED SOLUTIONS ARE PROPOSED BASED ON INCREASING THE IMPEDANCE OF POWER NETWORK LIKE FCLS OR SERIES REACTORS OR SPLIT BUS. THE APPROACH OF THIS PAPER IS CONTROLLING THE SOURCES OF THE FAULTS. IT PROPOSES A NEW SOLUTION FOR REDUCTION OF THE FAULT Current BY A controller. THE controller IS DESIGNED BY H ¥ MIXED-SENSITIVITY MINIMIZATION METHOD TO CONTROL THE FAULT Current THROUGH CONTROLLING THE FIELD Current OF THE GENERATOR.THIS METHOD IS SIMULATED ON A GENERATOR UNIT WHICH ITS EXCITER SYSTEM IS CONSIDERED FOR MODELING AND CONTROL DESIGN. THE RESULTS SHOW THAT THIS ECONOMICAL SOLUTION IS EFFICIENT ENOUGH.